\doxysection{BDMA\+\_\+\+Channel\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_b_d_m_a___channel___type_def}{}\label{struct_b_d_m_a___channel___type_def}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_b_d_m_a___channel___type_def_ae64e6fa9795e9cf60e93988c9da1a97b}{CCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_b_d_m_a___channel___type_def_a8b3eaea3e3ab6a598d1202f48b706154}{CNDTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_b_d_m_a___channel___type_def_a191a5e7c35694cc5c8f1e01a8aa4ea60}{CPAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_b_d_m_a___channel___type_def_a99ef9f96e0a3766cdd15bc943425d06d}{CM0\+AR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_b_d_m_a___channel___type_def_a9f1d5c8334a5fdc0f71d886ff4d5e2ec}{CM1\+AR}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_b_d_m_a___channel___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_b_d_m_a___channel___type_def_ae64e6fa9795e9cf60e93988c9da1a97b}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}!CCR@{CCR}}
\index{CCR@{CCR}!BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR}{CCR}}
{\footnotesize\ttfamily \label{struct_b_d_m_a___channel___type_def_ae64e6fa9795e9cf60e93988c9da1a97b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t BDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CCR}

DMA channel x configuration register \Hypertarget{struct_b_d_m_a___channel___type_def_a99ef9f96e0a3766cdd15bc943425d06d}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}!CM0AR@{CM0AR}}
\index{CM0AR@{CM0AR}!BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CM0AR}{CM0AR}}
{\footnotesize\ttfamily \label{struct_b_d_m_a___channel___type_def_a99ef9f96e0a3766cdd15bc943425d06d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t BDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CM0\+AR}

DMA channel x memory 0 address register \Hypertarget{struct_b_d_m_a___channel___type_def_a9f1d5c8334a5fdc0f71d886ff4d5e2ec}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}!CM1AR@{CM1AR}}
\index{CM1AR@{CM1AR}!BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CM1AR}{CM1AR}}
{\footnotesize\ttfamily \label{struct_b_d_m_a___channel___type_def_a9f1d5c8334a5fdc0f71d886ff4d5e2ec} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t BDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CM1\+AR}

DMA channel x memory 1 address register \Hypertarget{struct_b_d_m_a___channel___type_def_a8b3eaea3e3ab6a598d1202f48b706154}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}!CNDTR@{CNDTR}}
\index{CNDTR@{CNDTR}!BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CNDTR}{CNDTR}}
{\footnotesize\ttfamily \label{struct_b_d_m_a___channel___type_def_a8b3eaea3e3ab6a598d1202f48b706154} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t BDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CNDTR}

DMA channel x number of data register \Hypertarget{struct_b_d_m_a___channel___type_def_a191a5e7c35694cc5c8f1e01a8aa4ea60}\index{BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}!CPAR@{CPAR}}
\index{CPAR@{CPAR}!BDMA\_Channel\_TypeDef@{BDMA\_Channel\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CPAR}{CPAR}}
{\footnotesize\ttfamily \label{struct_b_d_m_a___channel___type_def_a191a5e7c35694cc5c8f1e01a8aa4ea60} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t BDMA\+\_\+\+Channel\+\_\+\+Type\+Def\+::\+CPAR}

DMA channel x peripheral address register 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
